The present invention relates to a semiconductor memory device with redundancy, that is, a memory device having auxiliary bits which may be substituted for defective bits.
FIGS. 1A and 1B respectively show a line decoder and an auxiliary line decoder of a conventional semiconductor memory device. By way of example, a redundancy dynamic MOS semiconductor memory device using a laser programming system will be described.
In FIG. 1A showing the line decoder, Q.sub.1 through Q.sub.5 designate insulated gate type field-effect transistors (MOS transistors), which have drains connected commonly to a node N.sub.1, sources connected to a ground terminal having a ground potential V.sub.ss and gates receiving respective address signals (RA.sub.2, RA.sub.2), through (RA.sub.6, RA.sub.6); Q.sub.6, an MOS transistor having a drain connected to a power supply terminal having a supply voltage V.sub.cc, source connected to the node N.sub.1, and a gate supplied with a prcharge signal PRD; Q.sub.7 through Q.sub.10, MOS transistors to the gates of which a separation signal CRDI is applied; Q.sub.11 through Q.sub.14, MOS transistors which have gates connected to sources of respective ones of the MOS transistors Q.sub.7 through Q.sub.10 and drains applied receiving word line drive signals CR.sub.0 through CR.sub.3 ; L.sub.1 through L.sub.4, links which are connected to the sources of corresponding ones of the MOS transistors Q.sub.11 and Q.sub.14 and which can be fused (rendered connected) by a laser; and WL.sub.n through WL.sub.n+3, word lines connected to the other ends of respective ones of the links L.sub.1 through L.sub.4.
The MOS transistors Q.sub.1 through Q.sub.10 form the line decoder and the MOS transistors Q.sub.11 through Q.sub.14 form a subdecoder and a word line drive circuit. The word line drive signals are those signals which are decoded by address signals (RA.sub.0, RA.sub.0) and (RA.sub.1, RA.sub.1) (not shown). The precharge signal PRD is used to precharge the line decoder. The separation signal CRDI is used to separate the node N.sub.1, which is the output terminal of the line decoder, from the gates of the MOS transistors Q.sub.11 through Q.sub.14.
In FIG. 1B showing the auxiliary line decoder, Q.sub.21 through Q.sub.26 designate MOS transistors which have drains connected commonly to the ground terminal at a ground voltage V.sub.ss, and gates supplies with respective one of the address signals RA.sub.0, RA.sub.1, . . . and RA.sub.5 ; Q.sub.27 through Q.sub.32, MOS transistors which have sources connected to the ground terminal at the ground potential V.sub.ss and gates supplies with respective ones of the address signals RA.sub.0, RA.sub.1 . . . and RA.sub.5 ; Q.sub.33, an MOS transistor having a drain connected to a node N.sub.2, source connected to the ground terminal at the ground voltage V.sub.ss and gate supplied with the address signal RA.sub.6 ; Q.sub.34, an MOS transistor having a drain connected to the power source terminal at the supply voltage V.sub.cc, source connected to the node N.sub.2, and gate supplied with the precharge signal PRD.
Further in FIG. 1B, Q.sub.35 designates an MOS transistor having a source connected to the node N.sub.2 and gates supplied with the separation signal CRDI; Q.sub.36, an MOS transistor having a drain supplied with a word line drive signal CR.sub.M and gate connected to the drain of the MOS transistor Q.sub.35 ; L.sub.11 through L.sub.16, links having first ends connected commonly to the node N.sub.2 and second ends connected to the sources of the MOS transistors Q.sub.21 through Q.sub.26, respectively, and which can be selectively fused by a laser; L.sub.17 through L.sub.22, links having first ends connected to the drains of the MOS transistors Q.sub.27 through Q.sub.32, respectively, and second ends connected commonly to the node N.sub.2 and which can be fused by a laser; and L.sub.23, a link which has one end connected to the source of the MOS transistor Q.sub.36 and the other end connected to an auxiliary word line SWL and which can be fused by a laser. The MOS transistor Q.sub.21 through Q.sub.35 form an auxiliary word line drive circuit. The node N.sub.2 acts as the output node of the auxiliary line decoder.
The operation of the semiconductor memory device thus constructed will be described. First, the case where no defective bits are present will be described. In this case, the links L.sub.1 through L.sub.4 are not fused. Accordingly, when the address signals (RA.sub.2, RA.sub.2), . . . (RA.sub.6, RA.sub.6) used to maintain the gates of the MOS transistors Q.sub.1 through Q.sub.5 at zero volts are applied, the MOS transistors Q.sub.1 through Q.sub.5 are nonconductive (off), and the node N.sub.1, which is the output terminal of the line decoder, is held at a high potential set thereupon by the precharge operation of the precharge signal PRD applied to the transistor Q.sub.6. On the other hand, a node connected to another line decoder (not shown) is held at the ground potential due to a discharging operation. When the high level separation signal CRDI is applied to the gates of the MOS transistors Q.sub.7 through Q.sub.10, the latter are rendered conductive. Therefore, the high potential of the node N.sub.1 is applied through the MOS transistors Q.sub.7 through Q.sub.10, which are thereby rendered conductive, to the gates of the MOS transistors Q.sub.11 through Q.sub.14, respectively. When the separation signal CRDI goes to the low level, the high gate potentials of the MOS transistors Q.sub.11 through Q.sub.14 are maintained at the respective gates. When one of the word line drive signals CR.sub.0 through CR.sub.3, for instance the signal CR.sub.1, is at a high potential, the MOS transistor Q.sub.12 is rendered conductive so that the high gate potential is transmitted through the MOS transistor Q.sub.12 and the link L.sub.2 to the word line WL.sub.n+1. As a result, data is read out of or written into a memory cell (not shown).
For instance, if a memory cell (not shown) connected to the word line WL.sub.n` includes a defective bit, the link L.sub.2 connected to the word line WL.sub.n+1 is opened (blown) by a laser so that the word line drive signal CR1 is not applied to the word line WL.sub.n+1. That is, data from the defective bit is not read nor written. In this case, one of the links forming each of the link pairs L.sub.11 and L.sub.17, L.sub.12 and L.sub.18, . . . and L.sub.16 and L.sub.22 is fused with a laser so that the MOS transistors Q.sub.21, . . . and Q.sub.35 of the auxiliary decoder are activated with combinations of signals for selecting the regular line decoder indicated in FIG. 1A. Therefore, the word line WL.sub.n+1 associated with the defective bit can be replaced by a normal auxiliary word line. In the case where no defective bit is involved, the auxiliary word line SWL will not be selected if the circuit is so designed that at least one of the MOS transistors Q.sub.21 through Q.sub.35 is rendered conductive by the signal at the node N.sub.2, which is the output terminal of the MOS transistors Q.sub.21 through Q.sub.35.
If the regular decoder of the conventional semiconductor memory device is defective, for instance, if the MOS transistor Q.sub.3 is damaged, the four word lines WN.sub.n through WN.sub.n+3 cannot be driven, and accordingly data cannot be written into or read out of the memory cells coupled to these word lines. Accordingly, if the area which the decoder occupies out of the entire area of the memory element is relatively large and the expected defective bit percentage is large, it is impossible to significantly increase the defect correction pecentage. In this point, the conventional semiconductor memory device is disadvantageous.